The present invention relates generally to semiconductor devices, and more particularly to power MOSFET devices.
Power MOSFET devices are employed in applications such as automobile electrical systems, power supplies, and power management applications. Such devices should sustain high voltage in the off-state while having a low voltage drop and high current flow in the on-state.
FIG. 1 illustrates a typical structure for an N-channel power MOSFET. An N-epitaxial silicon layer 1 formed over an N+ silicon substrate 2 contains p-body regions 5a and 6a, and N+ source regions 7 and 8 for two MOSFET cells in the device. P-body regions 5 and 6 may also include deep p-body regions 5b and 6b. A source-body electrode 12 extends across certain surface portions of epitaxial layer 1 to contact the source and body regions. The N-type drain for both cells is formed by the portion of N-epitaxial layer 1 extending to the upper semiconductor surface in FIG. 1. A drain electrode is provided at the bottom of N+ substrate 2. An insulated gate electrode 18 typically of polysilicon lies primarily over the portions of the drain at the surface of the device between the body regions, and separated from the body and drain by a thin layer of dielectric, often silicon dioxide. A channel is formed between the source and drain at the surface of the body region when the appropriate positive voltage is applied to the gate with respect to the source and body electrode.
The on-resistance of the conventional high voltage MOSFET shown in FIG. 1 is determined largely by the drift zone resistance in epitaxial layer 1. The drift zone resistance is in turn determined by the doping and the layer thickness of epitaxial layer 1. However, to increase the breakdown voltage of the device, the doping concentration of epitaxial layer 1 must be reduced while the layer thickness is increased. Curve 20 in FIG. 2 shows the on-resistance per unit area as a function of the breakdown voltage for a conventional MOSFET. Unfortunately, as curve 20 shows, the on-resistance of the device increases rapidly as its breakdown voltage increases. This rapid increase in resistance presents a problem when the MOSFET is to be operated at higher voltages, particularly at voltages greater than a few hundred volts.
FIG. 3 shows a MOSFET that is designed to operate at higher voltages with a reduced on-resistance. This MOSFET is disclosed in paper No. 26.2 in the Proceedings of the IEDM, 1998, p. 683. This MOSFET is similar to the conventional MOSFET shown in FIG. 2 except that it includes p-type doped regions 40 and 42 which extend from beneath the body regions 5 and 6 into the drift region of the device. The p-type doped regions 40 and 42 define columns in the drift region that are separated by n-type doped columns, which are defined by the portions of the epitaxial layer 1 adjacent the p-doped regions 40 and 42. The alternating columns of opposite doping type cause the reverse voltage to be built up not only in the vertical direction, as in a conventional MOSFET, but in the horizontal direction as well. As a result, this device can achieve the same reverse voltage as in the conventional device with a reduced layer thickness of epitaxial layer 1 and with increased doping concentration in the drift zone. Curve 25 in FIG. 2 shows the on-resistance per unit area as a function of the breakdown voltage of the MOSFET shown in FIG. 3. Clearly, at higher operating voltages, the on-resistance of this device is substantially reduced relative to the device shown in FIG. 1, essentially increasing linearly with the breakdown voltage.
The improved operating characteristics of the device shown in FIG. 3 are based on charge compensation in the drift region of the transistor. That is, the doping in the drift region is substantially increased, e.g., by an order of magnitude or more, and the additional charge is counterbalanced by the addition of columns of opposite doping type. The blocking voltage of the transistor thus remains unaltered. The charge compensating columns do not contribute to the current conduction when the device is in its on state. These desirable properties of the transistor depend critically on the degree of charge compensation that is achieved between adjacent columns of opposite doping type. Unfortunately, nonuniformities in the dopant gradient of the columns can be difficult to avoid as a result of limitations in the control of process parameters during their fabrication. For example, diffusion across the interface between the columns and the substrate and the interface between the columns and the p-body region will give rise to changes in the dopant concentration of the portions of the columns near those interfaces.
The structure shown in FIG. 3 can be fabricated with a process sequence that includes multiple epitaxial deposition steps, each followed by the introduction of the appropriate dopant. Unfortunately, epitaxial deposition steps are expensive to perform and thus this structure is expensive to manufacture. Another technique for fabricating these devices is shown in copending U.S. application Ser. No. 09/970,972, in which a trench is successively etched to different depths. A dopant material is implanted and diffused through the bottom of the trench after each etching step to form a series of doped regions (so-called xe2x80x9cfloating islandsxe2x80x9d) that collectively function like the p-type doped regions 40 and 42 seen in FIG. 3. However, the on-resistance of a device that uses the floating island technique is not as low as an identical device that uses continuous columns.
Accordingly, it would be desirable to provide a method of fabricating the MOSFET structure shown in FIG. 3 that requires a minimum number of epitaxial deposition steps so that it can be produced less expensively while also allowing sufficient control of process parameters so that a high degree of charge compensation can be achieved in adjacent columns of opposite doping type in the drift region of the device.
In accordance with the present invention, a method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and forming a voltage sustaining region on the substrate. The voltage sustaining region is formed in the following manner. First, an epitaxial layer is deposited on the substrate. The epitaxial layer has a first or a second conductivity type. Next, at least one terraced trench is formed in the epitaxial layer. The terraced trench has a trench bottom and a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls and bottom of the trench. A dopant of a conductivity type opposite to the conductivity type of the epitaxial layer is implanted through the barrier material lining the annular ledge and at the trench bottom and into adjacent portions of the epitaxial layer to respectively form at least one annular doped region and another doped region. The dopant is diffused in the annular doped region and the another doped region to cause the regions to overlap one another, whereby a continuous doped column is formed in the epitaxial layer. A filler material is deposited in the terraced trench to substantially fill the terraced trench. Finally, at least one region of conductivity type opposite to the conductivity type of the epitaxial layer is formed over the voltage sustaining region to define a junction therebetween.
In accordance with another aspect of the invention, the step of forming the terraced trench includes the steps of successively etching the plurality of portions of the terraced trench beginning with a largest width portion and ending with a smallest width portion. The smallest width portion may be located at a depth in the epitaxial layer such that it is closer to the substrate than the largest width portion.
In accordance with yet another aspect of the invention, the plurality of portions of the terraced trench are coaxially located with respect to one another.
Power semiconductor devices that may be formed by the present invention include, for example, a vertical DMOS, a V-groove DMOS, and a trench DMOS MOSFET, an IGBT, and a bipolar transistor.